LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gate is
port(

	clk: 		in std_logic;
	clkout_1s: 	out std_logic
);
end gate;

architecture bahave of gate is

signal count1: integer range 0 to 67500000;

begin

process(clk)------fenpin   预置1Hz
		begin
			if rising_edge(clk) then

				if count1 < 67500000 then
					count1 <= count1 +1;
				else 
					count1 <= 0;
				end if;
				
				if count1 <50000000 then 
					clkout_1s <= '1';				
					
				else 
					clkout_1s <= '0';
				
				end if;

         end if;
    end process;
   
    
end bahave;